The present invention relates to silicon-on-insulator (SOI) devices, and more particular to an SOI device which comprises at least a charge dissipation path abutting the various layers of the SOI device which substantially eliminates electrostatic charge from the substrate of an SOI device.
In semiconductor processing, SOI technology is becoming increasingly important since it permits the formation of high-speed integrated circuits. In SOI technology, a relatively thin layer of semiconducting material, e.g. Si, overlays a layer of insulating material (buried oxide region). This relatively thin layer of semiconducting material is generally the area wherein active devices are formed in SOI devices. Devices formed on SOI offer many advantages over their bulk Si counterparts, including higher performance, absence of latch-up, higher packing density and low voltage applications.
Despite the advantages obtained using SOI technology, SOI circuits, like other electronic devices, are susceptible to electrostatic discharge (ESD), i.e. a surge in voltage (negative or positive) that occurs when a large amount of current is applied in the circuit. Moreover, the handling of SOI devices themselves may lead to charging of the substrate.
To discharge electrostatic impulses, ESD protection schemes need a low voltage turn-on and a high current drive (the ability to generate or sink a large amount of current before a large amount of negative or positive voltage is developed). Traditional bulk overvoltage protection schemes, such as diodes, do not work well on SOI because of the presence of the relatively thin SOI buried oxide layer. That is, conventional diodes on SOI devices have small current drivability because the current is carried laterally (limited by the thickness of the semiconductor material).
One approach for protecting SOI circuitry from ESD is found in U.S. Pat. No. 4,989,057 to Lu. The Lu reference discloses a gated diode, which could be used for ESD design. The gate diode disclosed in Lu consists of a floating-body SOI transistor, with the gate connected to a signal pad. Although the diode disclosed in Lu can provide some ESD protection, the disclosed diode does not allow for obtaining ideal diode characteristics. Some reasons preventing ideal diode characteristics with the diodes disclosed in Lu include: (1) alignment tolerance of the substrate causes large process-induced variations; and (2) the conventional diode structure may be a polysilicon diode, which receives extensions and halo implants (implants normally utilized in deep sub-micron MOSFETs) that degrades the ideal characteristics on SOI.
Other ESD protection schemes for the front side of the SOI wafer are also known. Common to each is that the energy developed across prior art ESD protection schemes can be substantial. Thus, the heat generated by such ESD protection schemes must be dissipated by the relatively thin semiconducting layer. In cases wherein the heat becomes too excessive, destruction of the SOI circuit may occur.
In view of the above drawbacks with prior art ESD protection schemes, there is a need for developing new and improved ESD protection schemes that can be used for dissipating electrostatic charge from the substrate of an SOI wafer.
One object of the present invention is to provide an ESD protection scheme that can be used in dissipating the electrostatic charge from the substrate of an SOI wafer.
Another object of the present invention is to provide an ESD protection scheme that can be used with conventional back end of the line processing.
A still further object of the present invention is to provide an ESD protection scheme that eliminates charge discharge model (CDM) failure mechanisms, field induced-charging, and loss of control of backside of the SOI wafer which may, if not eliminated, result in parasitic turn-on of SOI bottom channel MOSFETs.
CDM failures are common concern in SOI devices when the substrate below the buried oxide layer is connected to a Vss power bus. Charge developed on the substrate below the buried oxide layer will occur due to the capacitance formed between the package and the substrate wafer. The stored charge may have a capacitance above 1000V. When the SOI substrate is connected to the Vss power bus rail and to a chip through a low resistance element surrounding the chip, any charge developed on the Vss will also be in electrical contact with any element that is connected to the Vss bus (N-channel sources, body-contacted MOSFETs, etc.). When the pin is grounded, the charge stored on the Vss power grid and the substrate will discharge through the physical element.
Another issue with SOI devices is that the contact is distributed so that the current is resistor ballasted through the substrate and the natural resistance of the substrate assists in the charge distribution and slows the speed of the rapid discharge.
In view of the above, another object of the invention is thus to provide an ESD protection scheme which can dissipate charge from the substrate of an SOI wafer to an alternative short path avoiding overvoltage or electrostatic overstress of SOI active devices, or discharge to the Vss ground power rail.
A yet further object of the invention is to decrease the rapid discharge path by introduction of resistive contacts to the substrate of an SOI wafer.
These and other objects and advantages are obtained in the present invention by utilizing a novel ESD protection scheme wherein a charge dissipation path abuts the interconnect level, the active device level, i.e. the semiconducting layer, the buried oxide (BOX) region and the substrate of an SOI device. Specifically, the present invention provides various methods and structures that can be used for dissipating the electrostatic charge from the substrate of an SOI device.
In accordance with one aspect of the present invention, a method of dissipating the electrostatic charge from a substrate of an SOI device is provided which comprises the steps of:
providing an SOI device, said SOI device comprising one or more interconnect levels, one or more active device regions, a buried oxide (BOX) region and a substrate; and
forming a charge dissipation path in said SOI device, wherein said charge dissipation path abuts the one or more interconnect levels, the one or more active device regions, the BOX region and the substrate of the SOI device.
The present method contemplates the utilization of high conductance materials, resistive means, and field emission or arc discharge means as possible charge dissipation paths. Combinations of the various kinds of charge dissipation paths are also contemplated herein.
In another aspect of the present invention, a structure for dissipating electrostatic charge from a substrate of an SOI device is provided. In accordance with this aspect of the present invention, the inventive structure comprises:
an SOI device comprising a substrate, a buried oxide layer formed on said substrate, a layer of semiconducting material, e.g. Si, formed on said buried oxide layer and an interconnect level formed on said layer of semiconducting material, said SOI device further comprising a charge dissipation path that abuts said interconnect level, said layer of semiconducting material, said buried oxide layer and said substrate.